A variety of technologies are known for single-level wafer-scale integration. However, some of these include integration of multiple chips but fail to address effective thermal management, which is a major issue in integrating multiple chips. The next step in the technological evolution is the multi-scale integration, particularly one that is easily scalable and this area is yet to be developed due to the compounding thermal management issues that come with this large multi-scale integration.
Historically, wire bonds have been used in the prior art for both connecting contacts on a chip to its package and also for chip to chip connections when multiple chips reside in a single package. In today's technologies, the wire bonds now are so large compared with the device geometries of modern integrated chips (ICs) that their size can make it difficult to couple modern ICs either with pins in the packaging in which the ICs reside or with neighboring ICs when multiple ICs are packaged together.
U.S. Pat. No. 8,617,927 which is incorporated herein, teaches a method of mounting electronic dies or chips into an electroformed heat spreader offering an integrated solution to thermal management at the single-level wafer-scale integration. U.S. application Ser. No. 15/169,591, incorporated herein, addresses another important technology in connecting die to package using electroplated and suspended interconnects over integrated heat spreaders. U.S. application Ser. No. 14/950,667 (141211), which is also incorporated herein, addresses another aspect of the single-level wafer-scale integration of direct IC-to-package wafer-level packaging with integrated thermal heat spreaders. While these technologies address various aspects of single-level wafer-scale integration while offering solutions to thermal management problems, there is a dire need to expand the scope to multi-level wafer-scale integration while at the same time solving the massive thermal management issues that come with this large scale multi-level integration.